1. Field of the Invention
The present invention relates to a simulation parameter extracting method of a MOS transistor.
2. Description of Related Art
In a simulation of a MOS transistor, a gate-overlap capacitance is one of physically important parameters. The gate-overlap capacitance is a capacitance of a part where the gate overlaps with the source or the drain in the MOS transistor. A gate-overlap capacitance value critically affects operation speed of a semiconductor device using a practical MOS transistor. Therefore, an accurate evaluation of the gate-overlap capacitance value has been desired.
To evaluate the gate-overlap capacitance, a TEG (Test Element Group) pattern is used. The TEG pattern includes the MOS transistor including the gate, the source and the drain. Further, contact plugs are formed on the source and the drain in the TEG pattern. The contact plugs are electrically connected to each of the source and the drain. A capacitance is measured by connecting a tester to the gate and the contact plug. The measured value obtained by the above-mentioned measurement includes a contact parasitic capacitance between the contact plug and the gate as well as the gate-overlap capacitance to be evaluated.
A method described below is known as a method to extract the gate-overlap capacitance from the measured value. First, the contact parasitic capacitance is evaluated by a simulation such as a TCAD (Technology Computer Aided Design) in the method. Next, the gate-overlap capacitance is calculated by subtracting a contact parasitic capacitance value evaluated by a simulation from the measured value including the contact parasitic capacitance. Even if it is impossible to neglect the effect of the contact parasitic capacitance when a distance between the contact plug and the gate is narrow, the gate-overlap capacitance can be calculated by the method.
A shape of the practical contact plug may be different for each wafer. To accurately evaluate the contact parasitic capacitance, it is necessary to observe a cross-sectional shape of a practically measured MOS transistor and input the cross-sectional shape thereof to a simulator. Therefore, it is necessary to expose the cross section of the measured TEG pattern to observe the cross-sectional shape of the practical MOS transistor. After exposing the cross section of the TEG pattern, it is impossible to measure the TEG pattern. Further, a process to observe the cross-sectional shape of the practical MOS transistor increases.
Furthermore, it is difficult to accurately input the cross-sectional shape of the MOS transistor to the simulator. Practically, only the shape change such as shape-expansion or shape-shrinkage is simply evaluated based on the shape of the contact plug obtained from the result of the cross-sectional observation. Then, the shape change is converted to a simple square pillar, and the simple square pillar is input to the simulator.
Therefore, the cross-sectional shape of the practical MOS transistor is different from the shape input to the simulator. Thus, it is considered that an error between the evaluated contact parasitic capacitance and the practical contact parasitic capacitance is caused. Even if the cross-sectional shape of the MOS transistor is accurately input, it is impossible to judge whether the contact parasitic capacitance is accurately evaluated or not.
Further, it is reported that the gate-overlap length is changed when a distance (gate space) between adjacent gates, or a distance between the gate and the contact plug, is changed. Especially, when the gate space is narrow, or the distance between the gate and the contact plug is narrow, the variation of the gate-overlap length stands out compared with the case of the gate space being wide. Therefore, it is desired that the method to extract the accurate overlap parasitic capacitance value when the gate space is narrow is achieved.
Furthermore, Japanese Unexamined Patent Application Publication No. 2008-225557 discloses a method to extract a diffusion layer resistance by a simulation using a diffusion layer resistor model. In Japanese Unexamined Patent Application Publication No. 2008-225557, a confirmation of extracting precision is performed by using a layout pattern in which the number and arrangement of contact plugs is changed.